Semester-wise syllabus for an M.Tech in VLSI Design

 

Semester 1:

Core Foundations

Courses: 

1. Digital VLSI Design

   - CMOS logic design, combinational/sequential circuits, timing analysis, and RTL design (Verilog/VHDL). 

2. Analog CMOS Design 

   - MOSFET operation, amplifiers, OP-AMPs, data converters, and noise analysis. 

3. Semiconductor Device Modeling 

   - PN junctions, MOS capacitors, SPICE models (BSIM), and process variations. 

4. FPGA-Based System Design 

   - FPGA architecture, synthesis, place-and-route, and prototyping (Xilinx/Intel tools). 

5. Research Methodology

   - Technical writing, data analysis (MATLAB/Python), and literature review. 

Labs: 

- Digital VLSI Lab (Cadence/Synopsys tools for RTL-to-GDSII flow) 

- FPGA Prototyping Lab (Verilog/VHDL projects on Xilinx Vivado/Quartus) 

 

Semester 2:

Specialization & Electives 

Core Courses:

1. ASIC Design and Verification 

   - ASIC flow, synthesis, static timing analysis (STA), and verification (UVM/SystemVerilog). 

2. Mixed-Signal IC Design

   - PLLs, ADCs/DACs, layout considerations, and signal integrity. 

Electives (Examples):

- Low-Power VLSI Design (sub threshold circuits, power gating, DVFS) 

- RF IC Design (RF amplifiers, mixers, LNA design) 

- VLSI Testing and DFT (BIST, scan chains, fault models) 

- Embedded Systems for VLSI (ARM cores, SoC integration) 

- Advanced Memory Design (SRAM, DRAM, emerging memories like RRAM) 

Labs: 

- ASIC Design Lab (Cadence Innovus, Synopsys Design Compiler) 

- Analog Layout Lab (Cadence Virtuoso for custom IC layout) 

 

Semester 3:

 Advanced Electives & Project Work 

Electives (Examples): 

- AI/ML for VLSI (ML-based optimization, EDA tool automation) 

- 3D IC and Packaging (TSV, interposer design, thermal management) 

- Hardware Security (side-channel attacks, PUF, secure IC design) 

- MEMS and Sensors (design, fabrication, and integration) 

- Quantum Computing Basics (qubit design, VLSI for quantum control) 

 

Project/Dissertation: 

- Phase 1: Topic selection (e.g., low-power IoT SoC, AI accelerator design, DFT for automotive ICs), literature review, and proposal. 

- Seminars: Presentations on trends like chiplets, neuromorphic engineering, or open-source EDA tools. 

 

Semester 4: Thesis/Project Completion 

Thesis/Project: 

- Full-time focus on design, simulation, tape-out (if applicable), or FPGA/ASIC implementation. 

- Final documentation, viva voce defense, and potential industry collaboration/publication. 

Additional Components:

- Industrial Internship (optional, with semiconductor firms like Intel, TSMC, or startups). 

- Workshops: Training in tools like Ansys HFSS (for RF), Machine Learning for EDA, or Silvaco TCAD. 

 

Elective Tracks (Specializations): 

1. Analog/RF IC Design 

   - High-frequency circuits, RF front-end design for 5G/IoT. 

2. Digital SoC Design

   - RISC-V cores, AI accelerators, and network-on-chip (NoC). 

3. VLSI for AI/ML Hardware 

   - Tensor cores, neuromorphic chips, and in-memory computing. 

4. VLSI Testing and Reliability 

   - DFT, aging effects, and radiation-hardened design.